Semiconductor devices are formed of multiple layers of materials overlaid over one another. Each of the layers may be referred to as a device level. Each of the layers is formed from a corresponding photomask. The photomask is produced from an associated design layout, typically provided in software such as GDS (Graphic Database System) or GDS II which is a database file format and the de facto industry standard for design layouts in the semiconductor manufacturing industry. At each device level, the design layout is used to ultimately produce a pattern in a corresponding layer of material.
Examples of device levels, each formed from an associated design layout, are active areas formed in a substrate, polysilicon or other semiconductor interconnect layers, metal or other conductive interconnect layers, and openings such as contacts, vias and trenches formed in dielectric layers. These are representative of various other device levels. In each design layout, there are different device regions that may represent different functional portions of the device, and/or different structural features. For any particular device level such as polysilicon, the density of the device features will vary depending on the device region and device structure. When the density of the device features is different throughout a device level, it adversely affects the process capability of operations performed on that and other layers. The density of device features in a device layer also impacts topographical and other concerns for the layers formed above and below the particular device level.
For example, a device such as a bandgap reference circuit may include bipolar junction transistors, BJT's, in one or more device regions on a die and resistors in other device regions of the same die. In the resistor areas, there may be a high density of device features at the polysilicon level, for example, and a low density of device features in the active area level whereas the bipolar junction transistor device regions may include a high density of features at the active area level and a low density of features at the polysilicon level.
It would be desirable to monitor the device feature density throughout device levels.